/*
 * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __RT5025_PMIC_H__
#define __RT5025_PMIC_H__
#include <power/pmic.h>
#include <fdtdec.h>

#define COMPAT_ROCKCHIP_RT5025  "rt,rt5025"
#define RT5025_I2C_ADDR 		0x35
#define RT5025_I2C_SPEED		200000
#define RT5025_NUM_REGULATORS		10

enum {
	RT5025_REG_DEVID,
	RT5025_REG_RANGE1START = RT5025_REG_DEVID,
	RT5025_REG_CHGCTL1,
	RT5025_REG_CHGCTL2,
	RT5025_REG_CHGCTL3,
	RT5025_REG_CHGCTL4,
	RT5025_REG_CHGCTL5,
	RT5025_REG_CHGCTL6,
	RT5025_REG_CHGCTL7,
	RT5025_REG_DCDCCTL1,
	RT5025_REG_DCDCCTL2,
	RT5025_REG_DCDCCTL3,
	RT5025_REG_VRCCTL,
	RT5025_REG_DCDCCTL4,
	RT5025_REG_LDOCTL1,
	RT5025_REG_LDOCTL2,
	RT5025_REG_LDOCTL3,
	RT5025_REG_LDOCTL4,
	RT5025_REG_LDOCTL5,
	RT5025_REG_LDOCTL6,
	RT5025_REG_RESV0,
	RT5025_REG_LDOOMS,
	RT5025_REG_MISC1,
	RT5025_REG_ONEVENT,
	RT5025_REG_DCDCONOFF,
	RT5025_REG_LDOONOFF,
	RT5025_REG_MISC2,
	RT5025_REG_MISC3,
	RT5025_REG_MISC4,
	RT5025_REG_GPIO0,
	RT5025_REG_GPIO1,
	RT5025_REG_GPIO2,
	RT5025_REG_RANGE1END = RT5025_REG_GPIO2,
	RT5025_REG_OFFEVENT = 0x20,
	RT5025_REG_RANGE2START = RT5025_REG_OFFEVENT,
	RT5025_REG_RESV1,
	RT5025_REG_RESV2,
	RT5025_REG_RESV3,
	RT5025_REG_RESV4,
	RT5025_REG_RESV5,
	RT5025_REG_RESV6,
	RT5025_REG_RESV7,
	RT5025_REG_RESV8,
	RT5025_REG_RESV9,
	RT5025_REG_RESV10,
	RT5025_REG_RESV11,
	RT5025_REG_RESV12,
	RT5025_REG_RESV13,
	RT5025_REG_RESV14,
	RT5025_REG_RESV15,
	RT5025_REG_IRQEN1,
	RT5025_REG_IRQSTAT1,
	RT5025_REG_IRQEN2,
	RT5025_REG_IRQSTAT2,
	RT5025_REG_IRQEN3,
	RT5025_REG_IRQSTAT3,
	RT5025_REG_IRQEN4,
	RT5025_REG_IRQSTAT4,
	RT5025_REG_IRQEN5,
	RT5025_REG_IRQSTAT5,
	RT5025_REG_RANGE2END = RT5025_REG_IRQSTAT5,
	RT5025_REG_IRQCTL = 0x50,
	RT5025_REG_RANGE3START = RT5025_REG_IRQCTL,
	RT5025_REG_IRQFLG,
	RT5025_REG_FGRESV1,
	RT5025_REG_VALRTMAX,
	RT5025_REG_VALRTMIN1,
	RT5025_REG_VALRTMIN2,
	RT5025_REG_TALRTMAX,
	RT5025_REG_TALRTMIN,
	RT5025_REG_VBATSH,
	RT5025_REG_VBATSL,
	RT5025_REG_INTEMPH,
	RT5025_REG_INTEMPL,
	RT5025_REG_FGRESV2,
	RT5025_REG_CONFIG,
	RT5025_REG_AINH,
	RT5025_REG_AINL,
	RT5025_REG_TIMERH,
	RT5025_REG_TIMERL,
	RT5025_REG_CHANNELH,
	RT5025_REG_CHANNELL,
	RT5025_REG_INACVLTH,
	RT5025_REG_INACVLTL,
	RT5025_REG_INUSBVLTH,
	RT5025_REG_INUSBVLTL,
	RT5025_REG_VSYSVLTH,
	RT5025_REG_VSYSVLTL,
	RT5025_REG_GPIO0VLTH,
	RT5025_REG_GPIO0VLTL,
	RT5025_REG_GPIO1VLTH,
	RT5025_REG_GPIO1VLTL,
	RT5025_REG_GPIO2VLTH,
	RT5025_REG_GPIO2VLTL,
	RT5025_REG_DCDC1VLTH,
	RT5025_REG_DCDC1VLTL,
	RT5025_REG_DCDC2VLTH,
	RT5025_REG_DCDC2VLTL,
	RT5025_REG_DCDC3VLTH,
	RT5025_REG_DCDC3VLTL,
	RT5025_REG_CURRH,
	RT5025_REG_CURRL,
	RT5025_REG_QCHGHH,
	RT5025_REG_QCHGHL,
	RT5025_REG_QCHGLH,
	RT5025_REG_QCHGLL,
	RT5025_REG_QDCHGHH,
	RT5025_REG_QDCHGHL,
	RT5025_REG_QDCHGLH,
	RT5025_REG_QDCHGLL,
	RT5025_REG_RANGE3END = RT5025_REG_QDCHGLL,
	RT5025_REG_DCDC4OVP = 0xA9,
	RT5025_REG_RANGE4START = RT5025_REG_DCDC4OVP,
	RT5025_REG_RANGE4END = RT5025_REG_DCDC4OVP,
	RT5025_REG_MAX,
};

#define RT5025_DCDCVOUT1	0x08
#define RT5025_DCDCVOUT2	0x09
#define RT5025_DCDCVOUT3	0x0a
#define RT5025_DCDCVOUT4	0x0b
#define RT5025_LDOVOUT1	0x0d
#define RT5025_LDOVOUT2	0x0e
#define RT5025_LDOVOUT3	0x0f
#define RT5025_LDOVOUT4	0x10
#define RT5025_LDOVOUT5	0x11
#define RT5025_LDOVOUT6	0x12

#define RT5025_DCDCVOUT_SHIFT1	2
#define RT5025_DCDCVOUT_SHIFT2	1
#define RT5025_DCDCVOUT_SHIFT3	2
#define RT5025_DCDCVOUT_SHIFT4	0
#define RT5025_LDOVOUT_SHIFT1	0
#define RT5025_LDOVOUT_SHIFT2	0
#define RT5025_LDOVOUT_SHIFT3	3
#define RT5025_LDOVOUT_SHIFT4	3
#define RT5025_LDOVOUT_SHIFT5	3
#define RT5025_LDOVOUT_SHIFT6	3

#define RT5025_DCDCVOUT_MASK1	0xFC
#define RT5025_DCDCVOUT_MASK2	0xFE
#define RT5025_DCDCVOUT_MASK3	0xFC
#define RT5025_DCDCVOUT_MASK4	0x0F
#define RT5025_LDOVOUT_MASK1	0x7F
#define RT5025_LDOVOUT_MASK2	0x7F
#define RT5025_LDOVOUT_MASK3	0xF8
#define RT5025_LDOVOUT_MASK4	0xF8
#define RT5025_LDOVOUT_MASK5	0xF8
#define RT5025_LDOVOUT_MASK6	0xF8

#define RT5025_DCDCEN_MASK1	0x01
#define RT5025_DCDCEN_MASK2	0x02
#define RT5025_DCDCEN_MASK3	0x04
#define RT5025_DCDCEN_MASK4	0x08
#define RT5025_LDOEN_MASK1	0x01
#define RT5025_LDOEN_MASK2	0x02
#define RT5025_LDOEN_MASK3	0x04
#define RT5025_LDOEN_MASK4	0x08
#define RT5025_LDOEN_MASK5	0x10
#define RT5025_LDOEN_MASK6	0x20


struct pmic_rt5025 {
	struct pmic *pmic;
	int node;	/*device tree node*/
	struct fdt_gpio_state pwr_hold;
};

#endif
